The present invention relates to a method of forming a semiconductor device, and more particularly to a chemical mechanical polishing method of polishing a metal layer to form interconnections in grooves formed in an insulating film over a silicon substrate, which is suitable for obtaining a highly accurate planarization.
As the requirement for further scaling down of advanced semiconductor devices has been on the increase, the importance of forming interconnections as fine as possible has also been on the increase. In order to form the fine interconnections, fine grooves as interconnection patterns are formed in an insulating film such as an inter-layer insulator for subsequent deposition of a metal layer such as an aluminum layer over an entire surface of the insulating film so that the fine grooves formed in the insulating film are filled with the metal layer before a chemical mechanical polishing of the metal layer is carried out to leave the metal layer only within the fine grooves, whereby the metal layers remaining within the fine grooves serve as metal interconnections.
In Japanese laid-open patent publication No. 6-313164, there is disclosed a conventional chemical mechanical polishing method for polishing a metal layer overlying an insulating film surface having fine grooves so as to form fine metal interconnections within the fine grooves in the insulating film. FIG. 1A is a fragmentary cross sectional elevation view illustrative of a metal layer overlying a surface having fine grooves of an inter-layer insulator over a silicon substrate in a first step in sequential processes involved in a conventional chemical mechanical polishing method. FIG. 1B is a fragmentary cross sectional elevation view illustrative of a metal layer overlying a surface having fine grooves of an inter-layer insulator over a silicon substrate in a second step in the sequential processes involved in the conventional chemical mechanical polishing method.
With reference to FIG. 1A, an inter-layer insulator 22 having a thickness of about 1 micrometer is formed over a silicon substrate 21 by a thermal oxidation of silicon method or a chemical vapor deposition method. Grooves 23 serving as interconnection patterns are then formed in a surface of the inter-layer insulator 22. A metal layer 24 is deposited by a sputtering method onto an entire surface having the grooves 23 of the inter-layer insulator 22 so that the grooves 23 are completely filled with the metal layer 24 and also the metal layer 24 overlies the surface of the inter-layer insulator 22.
With reference to FIG. 1B, a surface of the metal layer 24 is subjected to a chemical mechanical polishing, wherein this chemical mechanical polishing method is carried out by use of a polishing material which has been prepared as follows. A colloidal silica slurry is diluted with a pure water to form an aqueous slurry before this aqueous slurry is then added with a polishing promoter which consists of both hydrogen peroxide and either sodium persulfate or potassium persulfate, thereby preparing the polishing material to be used for the chemical mechanical polishing. A non-woven fabric polish pad is also used as a polish pad. The metal layer 24 is polished to remain only within the grooves 23, whereby interconnection layers 26, 26a and 26b are formed within the grooves 23.
The above chemical mechanical polishing method is advantageous in being highly efficient without generation of surface defects such as scratch, but is disadvantageous in over-polishing of the metal layer 24 to form an over-polished portion 25 on a region having a high density of the interconnection layers 26, for example, a center region of the semiconductor chip, whilst peripheral regions having a low density of the interconnection layers 26a and 26b are free of the over-polished portion 25.
Namely, the polishing rate or the polishing efficiency of the above conventional chemical mechanical polishing method is likely to be higher on the high density region having the high density of the interconnections 26 than on the low density region having the low density of the interconnections 26a 26b, for which reason, on the high density region of when the high density of the interconnections 26, over-polishing is likely to appear, whereby upper portions of the interconnection layers 26 within the grooves 23 on the high density region having the high density of the interconnections 26 are also likely to be over-polished, resulting in formation of the over-polished portion 25 on the high density region having when the high density of the interconnections 26. As a result, the interconnection layers 26 formed on the high density region are thinner than the interconnection layers 26a and 26b formed on the low density regions. Namely, the above conventional chemical mechanical polishing method causes variations in thickness of the interconnection layers in the grooves due to variation in density of when the interconnection layers over the semiconductor chip. If, further, variations in the polishing rate or polishing efficiency of the metal layer depend upon variation in density of the interconnection layers, then this means that he variations in the polishing rate or polishing efficiency of the metal layer certainly depend upon variations in width of the interconnection layers even a pitch of the interconnection layers remains constant over the semiconductor chip. Namely, variations in thickness of the interconnection layers depend upon the variation in width of the interconnection layers. If the widths of the interconnection layers are varied over the semiconductor chip, then the thickness of when the interconnection layers are also varied over the semiconductor chip.
In the above circumstances, it had been required to develop a novel method of polishing a metal layer to form interconnections in grooves formed in an insulating film over a substrate free from the above disadvantages.